DVCon U.S., the annual conference for design and verification professionals, is scheduled for February 24 – 27, 2025 in San Jose, California.
Overview of DVCon U.S. 2025
Bringing together industry leaders and technical experts, this event is dedicated to the discussion of functional design and verification of electronic systems. The sessions planned for DVCon U.S. 2025 cover a wide range of key topics including verification methodologies, hardware design, low-power design and power optimization strategies. There will be a strong focus on chip design and the role of AI and ML in verification, exploring how these ever-evolving technologies are transforming traditional processes.
- Dates: February 24 – 27, 2025
- Venue: DoubleTree by Hilton Hotel, San Jose, California
- Sponsors include: Cadence, Synopsys, Siemens, Lubis EDA, Keysight Technologies, Chipright
DVCon Panel: Are AI Chips Harder to Verify?
This panel brings together verification experts from across the industry to share their unique experiences and insights. Together they will address the critical question “Are AI Chips Harder to Verify” and explore how different business models and market demands shape their verification strategies.
Moderated by Moshe Zalcberg, CEO of Veriest Solutions, the panelists are:
- Harry Foster, Chief Scientist Verification, Siemens EDA
- Ahmad Ammar, Technical Lead, AIM (AI, Infrastructure, and Methodology), AMD
- Stuart Lindsay, Principal HW EDA Methodology Engineer, Groq
- Shahriar Seyedhosseini, Generalist Engineer, MatX
Key topics of discussion will include coverage metrics for AI workloads, verification reuse across multiple configurations, system-level aspects, the balance between traditional verification methods, and the potential for AI-assisted approaches.
Pioneering Ideas: DVCon Keynote Sessions
Keynote sessions will deliver valuable insights into cutting-edge solutions shaping the future of chip design and innovation:
- AI-driven Era of Pervasive Intelligence Necessitates New Design, Optimization and Verification Struggles: Attendees of this keynote, delivered by Synopsys and Microsoft, should expect to gain actionable insights into advanced methodologies for balancing complexity, cost, and time to value (TTV). The session will explore strategies to tackle AI-driven innovation challenges across the electronics landscape, from design optimization to system-level solutions.
- The Role of EDA in U.S. Economic Security: In this talk, Robert Aitken from CHIPS R&D is expected to explore the pivotal role of electronic design automation (EDA) has in enabling the semiconductor revolution and supporting the U.S. leadership role in chip design. The presentation will explore the history of EDA, the challenges it faces today in America, and how initiatives like CHIPS for America and its CHIPS national Advanced Packaging Manufacturing Program is helping to address the challenges going forward.
“I am particularly excited about the engaging keynotes and panel topics we’ve lined up for attendees this year,” said Tom Fitzpatrick, DVCon U.S. 2025 General Chair. “Each topic is not only compelling, but also relevant to the challenges and opportunities our industry faces today. I’m confident attendees will gain valuable insights and leave with much to consider as the industry continues to evolve.”
Tutorials & Workshops at DVCon U.S. 2025
The aim of the conference is to bring chip architects, design and verification engineers, and IP integrators together to explore the latest methodologies, techniques, applications, and demonstrations for the practical use of EDA solutions for electronic design. Beyond the panel discussions and keynote presentations, attendees can also look forward to a wide range of expert-led tutorial and workshop sessions including:
Verification Methodologies & Innovations
- Next-Gen Verification Technologies for Processor-Based Systems – Synopsys
- Complex Verification Example: RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SOC platforms – Breker
- Step Function Leaps in RTL Functional Verification Powered by AI/ML Innovations – Siemens
- Accelerating Functional Verification with Machine Learning – Texas A&M University
- Accelerating Design & Verification with AI Agents – ChipAgents AI
Hardware Design and Alternate Representation
- Beyond Integers and Floating Point – Designing and Verifying with Alternate Number Representations – Siemens
- Modernizing the Hardware / Software Interface – Life beyond spreadsheets. How to bring your SoC register design into the 21st Century – Arteris IP
Low-Power Design and Power Optimization
- Emulation Driven Power Estimation for Real World Applications – Cadence
- Moving Application-level Power Optimization to Pre-silicon with Advanced Hybrid Emulation and Power Exploration Technologies – Synopsys
- Power Dynamics: Shaping the future of the data centric era – Siemens
- Introduction of IEEE 1801-2024 (UPF4.0) improvements for the specification and verification of low-power intent – Accellera
Standards and Interoperability
- IP-XACT Workshop at DVCon US 2025 – Accellera
- CDC/RDC Interchange Format Standard – Accellera
Specialized Design and Signoff Techniques
- Comprehensive Glitch Signoff – Learnings and experiences from industry use cases – Real Intent
- PSS case studies in real-life projects – Cadence
- PSS Comes of Age: Runtime Behavioral Coverage, Methodology and More – Accellera
Exploring the Future of Design & Verification
With DVCon U.S. 2025 preparing to bring together professionals to explore the future of design and verification, it’s also worth mentioning DVCon Europe – scheduled for later on this year in Germany and with a similar focus on cutting-edge methodologies and industry trends, the conference will offer another exciting opportunity for experts to gather, network, and share insights.
As always, this year’s edition of DVCon U.S. will focus on the practical aspects of design and verification of electronic systems and integrated circuits. “Attending the Design and Verification Conference and Expo offers an opportunity to learn about the latest advancements in design and verification technologies, as well as gain insight into emerging standards and strategies for tackling current challenges” said Tom Fitzpatrick, DVCon U.S. 2025 General Chair. “Our commitment is to provide attendees with an exceptional technical program, fostering invaluable face-to-face connections among colleagues, a longstanding hallmark of DVCon.”
Visit the DVCon U.S. website for further information on the Program Grid, Steering Committee, Registration, Sponsors and Exhibitors and stay tuned with their LinkedIn for the latest updates.