Accellera Systems Initiative has officially approved Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard for release and immediate download.
What is UVM-MS 1.0?
UVM-MS 1.0 establishes a standardized methodology for analog/mixed-signal verification, building on the UVM IEEE 1800.2 standard. This methodology enhances AMS verification by enabling the reuse of proven components, leading to increased productivity, improved quality and streamlined workflows.
By leveraging existing classes, UVM-MS extends digital-centric UVM to facilitate the creation of mixed-signal testbenches and components. This integration enables smooth interaction between class-based and structural environments for optimal results.
Key Innovation: MS Bridge
UVM-MS 1.0 introduces the MS Bridge, a SystemVerilog module that seamlessly connects UVM agents to mixed-signal Designs Under Test (DUT). It includes an MS Proxy class, which provides an API for controlling the core of the bridge.
The MS Bridge manages key functions such as datatype conversion and signal manipulation, enabling smooth communication between analog and digital simulators. This reduces the need for custom AMS-DMS interfaces, improving co-simulation efficiency and streamlining the verification process.
Overall, it reduces reliance on manual interfaces, enabling smoother workflows, faster setup, and improved accuracy when handling complex mixed-signal designs.
The MS Bridge and other UVM-MS components facilitate a seamless connection between analog and digital within the UVM methodology.
Industry Impact & Future Outlook
Tom Fitzpatrick, Chair of the UVM-MS Working Group, described the release of UVM-MS as “a game changer for the verification of AMS designs” and explained:
“This unified approach will help to make the verification of components and subsystems much more efficient and enable the development of reusable UVM-MS verification components, similar to Verification IP available today in UVM for digital verification. I’m deeply grateful for the hard work and collaboration of our working group members whose expertise made this achievement possible.”
As EDA vendors and the broader semiconductor industry work to integrate UVM-MS, several key benefits are expected, including:
- Accelerated AMS verification cycles
- Improved alignment with modern SoC development workflows
- Wider adoption of standardized AMS verification methodologies
Accellera has confirmed the long-term goal for UVM-MS is to transition to the IEEE Design Automation Standards Committee (DASC) for formal standardization. The transition to formal IEEE standardization will not only elevate UVM-MS’s global standing but also pave the way for further innovations in mixed-signal verification methodologies.
For more details, visit the Accellera Systems Initiative website.
Further Reading:
1800.2-2020 – IEEE Standard for UVM Language Reference Manual