Accellera’s Approval of UVM-MS 1.0: A Milestone in Mixed-Signal Verification
Accellera Systems Initiative has officially approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard. This release is now available for immediate download. UVM-MS 1.0 establishes a standardized methodology for analog and mixed-signal (AMS) verification, building on the UVM IEEE 1800.2 standard. This methodology enhances AMS verification by enabling the reuse of proven components, leading to increased productivity, improved quality and streamlined workflows.
Key features of UVM-MS 1.0
- Unified Testbench Environment: Combines analog and digital verification for streamlined workflows
- Improved Efficiency: Reduces manual effort in mixed-signal verification tasks, accelerating design cycles
- Scalability: Supports the verification of complex, large-scale systems, making it suitable for a diverse range of applications
- Standardized Approach: Provides a consistent methodology across projects, ensuring reliability and reducing errors
The MS Bridge: Seamless Interaction Between UVM Agents & Mixed Signal DUTs
One of the key innovations introduced with UVM-MS is the MS Bridge, a SystemVerilog module designed to connect UVM agents to mixed-signal Designs Under Test (DUT). This new component includes an MS Proxy class and provides an API to manage functions like datatype conversion and signal manipulation. By simplifying communication between analog and digital simulators, the MS Bridge reduces the need for custom AMS-DMS interfaces, improving co-simulation efficiency and streamlining verification workflows.
How will UVM-MS Impact Mixed-Signal Verification?
UVM-MS empowers teams with faster, more reliable and cost-effective verification processes, cutting time-to-market for advanced semiconductor designs. By leveraging UVM-MS, engineers are equipped with a robust toolset to tackle the increasinging complexities of modern mixed-signal verification.
Tom Fitzpatrick, Chair of the UVM-MS Working Group, describes UVM-MS as “a game changer for the verification of AMS designs.” He adds, “This unified approach will help to make the verification of components and subsystems much more efficient and enable the development of reusable UVM-MS verification components, similar to Verification IP available today in UVM for digital verification.”
Key Benefits of UVM-MS for the Semiconductor Industry
As EDA vendors and the broader semiconductor industry work to integrate UVM-MS, several key benefits are expected, including:
- Accelerates AMS verification cycles
- Aligns with modern SoC development workflows
- Promotes wider adoption of standardized AMS methodologies
Accellera plans to transition UVM-MS to the IEEE Design Automation Standards Committee (DASC) for formal standardization. Achieving this will raise its global standing and pave the way for future innovations in mixed-signal verification methodologies.
To learn more and download UVM-MS 1.0, visit the Accellera Systems Initiative website.