Marvell has successfully demonstrated its next-generation 2nm silicon IP platform, designed to boost AI and cloud infrastructure innovation. Built on TSMC’s cutting-edge 2nm process, the platform provides key components for cloud providers to accelerate operations and develop custom AI accelerators, CPUs, optical DSPs, switches and more.
The Shift to 2nm Silicon
As the demand for artificial intelligence (AI), next-generation data centers and high-performance computing (HPC) continues to rise, the need for enhanced power efficiency and processing capabilities becomes more critical. The transition to 2nm technology, which features smaller transistors, addresses these needs by boosting performance and improving energy efficiency. Companies like Marvell and TSMC are actively developing advanced solutions capable of powering the next wave of technological innovations.
“TSMC is pleased to collaborate with Marvell on the development of its 2nm platform and the delivery of its first silicon,” said Dr. Kevin Zhang, senior vice president of business development and global sales, and deputy co-chief operating officer at TSMC. “We look forward to our continued collaboration with Marvell to utilize TSMC’s best-in-class silicon technology process and packaging technologies to advance accelerated infrastructure for the AI era.”
Meeting the Demand for Custom Silicon
To meet the increasing demand for custom silicon, Marvell is developing a comprehensive semiconductor IP portfolio, which includes:
- Electrical and optical serializer/deserializer (SerDes)
- Die-to-die interconnects for 2D and 3D devices
- Advanced packaging technologies
- Silicon photonics
- Custom high-bandwidth memory (HBM) compute architecture
- On-chip static random-access memory (SRAM)
- System-on-Chip (SoC) fabrics
- PCIe Gen 7 compute fabric interfaces
According to Sandeep Bharathi, Chief Development Officer at Marvell, this platform approach allows the company to “accelerate the development of market-leading high-speed SerDes and other critical technologies on the latest process manufacturing nodes”, enabling faster development of XPUs and other accelerated infrastructure technologies.
Unlocking Design Flexibility with 3D I/O Technology
Marvell’s 2nm silicon platform also introduces significant benefits for chip designers with its 3D simultaneous bi-directional I/O. This new technology is particularly beneficial as chiplet-based designs are becoming more common. By connecting vertically stacked die within chiplet architectures, designers can achieve higher bandwidth and greater design flexibility. Operating at speeds up to 6.4 Gbits/second, the bi-directional I/O enhances data transfer efficiency, doubling bandwidth and reducing connections by up to 50%. According to Marvell, this innovation helps designers build taller, more capable stacks, offering more functionalities than traditional monolithic silicon devices, while maintaining the functionality of a single unit.
Accelerated Infrastructure for the AI Era
As AI, cloud computing, and next-gen data centers evolve, companies are pushing the boundaries of semiconductor innovation. Marvell, TSMC and other industry leaders will work to accelerate AI applications by enabling faster, more efficient custom silicon development. According to Marvell, custom silicon will account for 25% of the accelerated compute market by 2028. The company says its silicon IP portfolio will play a key role in advancing AI innovation and powering its foundations.
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