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Senior Verification Engineer
Senior Verification Engineer
Role Description
B.Sc./M.Sc in Electrical Engineering / Computer Science
Minimum 5 years of experience in SoC Verification
Knowledge and experience in System Verilog or āeā (Specman) languages.
Deep familiarity with one or more of the following verification methodologies: eRM/UVM/OVM
Vast knowledge of verification flow ā (block level and full chip verification)
Dynamic, quick learner, able to take ownership of complex tasks, team player
Fluent in English
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